1. Field of the Invention
The present invention is directed to an interface circuit that allows 256k.times.16 bit dynamic random access memories (DRAMs) from different manufacturers to be used as desired by system designers and, more particularly, to an interface circuit that adapts memory location selection and strobe signals to two different types of DRAMs by selectably producing column address strobes and/or low and high byte selection signals as necessary to allow writing into either or both 8 bit bytes of a 16 bit word.
2. Description of the Related Art
In general, 256K.times.16 bit DRAMs are available in two configurations. In both configurations, there are nine or more address pins, which are multiplexed by row-address strobe (RAS) and column address strobe (CAS) signals to form eighteen address bits. To address a location within the DRAM, one group of bits of the address are applied to the address pins, and are latched into the DRAM on the falling edge of the RAS. Then the remaining group of bits of the address are applied to these same address pins and are then latched into the DRAM on the falling edge of the CAS. Thus, eighteen address bits are latched into the DRAM, allowing any one of 262,144 (256K) 16 bit wide locations to be addressed.
However, in 256K.times.16 bit DRAMS it is often desired to be able to select only the lower byte, only the upper byte, or both bytes of the 16 bit data word when writing to the DRAM. In general, this selection is not required when reading, as the extra byte may simply be ignored. This selection ability is important when writing to the DRAM, otherwise the data in the extra byte would be destroyed by overwriting it with unwanted data. This is particularly important in video pixel processing operations where pixels are eight bits. Manufacturers of the DRAMs have provided two different means for selecting which (or both) bytes are written. One method is to provide two CAS pins, one for the low byte and one for the high byte. The other method is to provide two write pins, one for the low byte and one for the high byte. Writing to a byte only occurs when the appropriate write pin is held low for sufficient setup and hold times relative to the falling edge of the appropriate CAS lines.
Some manufacturers provide such DRAMs with 2 CAS pins and one write pin for, example the 514160 JP/ZP from Hitachi, others provide DRAMs with one CAS pin and two write pins, for example the M5M44160AJ from Mitsubishi. At least one manufacturer provides DRAMs in both configurations, for example the NEC 4241600 and NEC 4241610 from NEC. The DRAMs configured with one of these sets of selection signals is not interchangeable with DRAMS configured with the other set of selection signals. The DRAMS are interchangeable in all other respects since they use the same memory location address signals, etc. Incidentally, if the two CAS lines are provided for the DRAM, they may also be used in selectively enabling the output of either or both bytes during reading.
Because DRAMs are commodity items, it is desirable to have maximum flexibility in selecting the DRAM vendor. Thus, a means of easily configuring a system during manufacture to be able to use either style of DRAM is desirable.